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CHIP DESIGN FOR SUBMICRON VLSI : CMOS LAYOUT AND SIMULATION

UYEMURA, JOHN P.,

CHIP DESIGN FOR SUBMICRON VLSI : CMOS LAYOUT AND SIMULATION - DELHI: CENAGE NEW LEARNING, 2013. - 411: 21CM+ PB.

RUSA MDC GRANT 2014-2017

Subjects--Index Terms: Chip Design

Dewey Class. No.: 621.3815 UYE

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