UYEMURA, JOHN P., <br/><br/>
CHIP DESIGN FOR SUBMICRON  VLSI : CMOS LAYOUT AND SIMULATION 

 - DELHI:  CENAGE NEW LEARNING,  2013. 
 - 411:  21CM+  PB. 
<br/><br/> RUSA MDC GRANT 2014-2017 
<br/><br/><label>Subjects--Index Terms: </label>Chip Design 
<br/><br/><label>Dewey Class. No.: </label>621.3815 UYE