000 00491cam a2200181ua 4500
001 22576
008 180306n II |||gr||||Z||||||eng
040 _aMAIN
041 _aEnglish
082 _a621.3815 UYE
100 _aUYEMURA, JOHN P.,
_eAUTHOR.
245 1 _aCHIP DESIGN FOR SUBMICRON VLSI : CMOS LAYOUT AND SIMULATION
260 _aDELHI:
_bCENAGE NEW LEARNING,
_c2013.
300 _a411:
_c21CM+
_ePB.
500 _aRUSA MDC GRANT 2014-2017
653 _aChip Design
942 _cBK
999 _c22436
_d22436